Verilog assign statement

Hardware schematic.

Signals of type wire or a similar wire like data type requires the continuous assignment of a value. For example, consider an electrical wire used to connect pieces on a breadboard. As long as the +5V battery is applied to one end of the wire, the component connected to the other end of the wire will get the required voltage.

breadboard-circuit

In Verilog, this concept is realized by the assign statement where any wire or other similar wire like data-types can be driven continuously with a value. The value can either be a constant or an expression comprising of a group of signals.

Assign Syntax

The assignment syntax starts with the keyword assign followed by the signal name which can be either a single signal or a concatenation of different signal nets. The drive strength and delay are optional and are mostly used for dataflow modeling than synthesizing into real hardware. The expression or signal on the right hand side is evaluated and assigned to the net or expression of nets on the left hand side.

Delay values are useful for specifying delays for gates and are used to model timing behavior in real hardware because the value dictates when the net should be assigned with the evaluated value.

  • LHS should always be a scalar or vector net or a concatenation of scalar or vector nets and never a scalar or vector register.
  • RHS can contain scalar or vector registers and function calls.
  • Whenever any operand on the RHS changes in value, LHS will be updated with the new value.
  • assign statements are also called continuous assignments and are always active

In the following example, a net called out is driven continuously by an expression of signals. i1 and i2 with the logical AND & form the expression.

assign-flash-1

If the wires are instead converted into ports and synthesized, we will get an RTL schematic like the one shown below after synthesis.

verilog assign 1'b0

Continuous assignment statement can be used to represent combinational gates in Verilog.

The module shown below takes two inputs and uses an assign statement to drive the output z using part-select and multiple bit concatenations. Treat each case as the only code in the module, else many assign statements on the same signal will definitely make the output become X.

Assign reg variables

It is illegal to drive or assign reg type variables with an assign statement. This is because a reg variable is capable of storing data and does not require to be driven continuously. reg signals can only be driven in procedural blocks like initial and always .

Implicit Continuous Assignment

When an assign statement is used to assign the given net with some value, it is called explicit assignment. Verilog also allows an assignment to be done when the net is declared and is called implicit assignment.

Combinational Logic Design

Consider the following digital circuit made from combinational gates and the corresponding Verilog code.

combinational-gates

Combinational logic requires the inputs to be continuously driven to maintain the output unlike sequential elements like flip flops where the value is captured and stored at the edge of a clock. So an assign statement fits the purpose the well because the output o is updated whenever any of the inputs on the right hand side change.

After design elaboration and synthesis, we do get to see a combinational circuit that would behave the same way as modeled by the assign statement.

combinational gate schematic

See that the signal o becomes 1 whenever the combinational expression on the RHS becomes true. Similarly o becomes 0 when RHS is false. Output o is X from 0ns to 10ns because inputs are X during the same time.

combo-gates-wave

Click here for a slideshow with simulation example !

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Are '0' and '1'b0' different in verilog?? (using Synopsys DC)

  • Thread starter minho_ha
  • Start date Jun 8, 2016
  • Jun 8, 2016

Junior Member level 3

Are '0' and '1'b0' different in verilog using synopsys DC?? When i used '0' in Xilinx synthesis tool (ISE and Vivado), there was no error. Using synopsys DC, I got elaborate error using verilog code which is running well in Xilinx tool. The only thing i can infer is using '0' instead of using '1'b0'. If they are same in verilog, i should found other reason. Help, plz.  

dpaul

Advanced Member level 5

Using synopsys DC, I got elaborate error using verilog code which is running well in Xilinx tool Click to expand...
dpaul said: That can happen! Just be disciplined in your RTL code to avoid such errors. If a single bit single needs to be reset use 1'b0 for a 4-bit signal use 4'b0000 and so on (you can also use 4'h0 for signal with larger widths). Click to expand...

ThisIsNotSam

minho_ha said: Are '0' and '1'b0' different in verilog using synopsys DC?? When i used '0' in Xilinx synthesis tool (ISE and Vivado), there was no error. Using synopsys DC, I got elaborate error using verilog code which is running well in Xilinx tool. The only thing i can infer is using '0' instead of using '1'b0'. If they are same in verilog, i should found other reason. Help, plz. Click to expand...
ThisIsNotSam said: verilog rules dictate that your '0' will be expanded to as many bits as needed. it is generally considered a bad practice that will yield warnings from DC, RC, HAL, LEC, and so on. Click to expand...

ads-ee

Super Moderator

0 is an integer constant in Verilog it is normally interpreted as a 32-bit integer by many simulators and 64-bit on some simulators that run on 64-bit systems. You can expect to have errors if you use this in places where you should know the exact bit width. Port assignments will either cause warnings of mismatched widths between the declared width and the width of the data in the port mapping or errors in the case of DC. Assignments such as: assign some_signal[7:0] = 0; should work fine on any simulator or synthesis tool as assigning something of a larger width to a smaller width variable results in truncation of the value in Verilog (along with a bunch of warnings).  

minho_ha said: Can '0' cause error?? not warning. Click to expand...
ThisIsNotSam said: we can argue whether it should be an error or warning but there is little merit to it. it's a simple mistake to fix. Click to expand...
Xilinx are you listening...they are notorious for leaving this kind of stuff in their IP code. Click to expand...
  • Jun 9, 2016

Full Member level 5

Your current goal is "no error" in any tool, it should be change to "a good coding style". I think you should read some rules/style of verilog for synthesis. For example: http://www.ee.ncu.edu.tw/~jfli/vlsidi/lecture/Verilog-2012.pdf "Importance of Coding Style  Make sure your code is readable, modifiable,and reusable  Good coding style helps to achieve better results in synthesis and simulation"  

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  1. Verilog Assign Statement

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COMMENTS

  1. What is the best way to write bit number in Verilog?

    In SystemVerilog, if you want to set all bits of a variable to 0, you write VariableName = '0; The expression '0 will be sized to the context of the variable it is being assigned to. There is no need to declare a specific width.

  2. Parametric bit-width assignment in Verilog

    CODE <= {BUS_WIDTH{1'b0}}; CODEreg <= {BUS_WIDTH{1'b0}}; Refer to IEEE Std 1800-2017, section 11.4.12.1 Replication operator. The one bit value (1'b0) is replicated 8 times to form the 8-bit value (8'b0000_0000). This is synthesizable. ... Difference between blocking and nonblocking assignment Verilog. 7.

  3. What is supposed to happen in Verilog if a signal of one width is

    What is supposed to happen in Verilog if a signal of one width is assigned to another signal of a different width? Ask Question Asked 7 years, 1 month ago Modified 7 years, 1 month ago Viewed 18k times 4 As in these two cases: wire [3:0] A, B; wire [4:0] C, D; assign A = C; // larger width to smaller width

  4. Assigning a zero to a vector in Verilog

    1 Answer Sorted by: 1 SystemVerilog has the bit fill literals '0, '1, 'x, and 'z. This means fill a vector with a digit to whatever width is required by the context. (In a self-determined context, it is just a single bit) You should write: assign x = '0; Share Cite Follow edited Sep 14, 2020 at 0:39 answered Sep 14, 2020 at 0:23 dave_59

  5. Verilog assign statement

    Example #1 Example #2 Assign reg variables Implicit Continuous Assignment Combinational Logic Design Hardware Schematic Signals of type wire or a similar wire like data type requires the continuous assignment of a value. For example, consider an electrical wire used to connect pieces on a breadboard.

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    Verilog - Operators Some More Lexical Conventions I The order of execution of the assign statements is unknown I We must fake parallel execution... gates operate in parallel I The assign statements " re" when the RHS variables change I RHS = a, b, in1, in2, sel I The values of a, b, and z are updated at the end of the timestep

  9. Procedural blocks in verilog

    initial begin a = 1'b0; b = 1'b1; end Will the assignment of b will take place a small time after the assignment of a? If not what will be the difference between this and the concurrent blocks in verilog, i.e.,assign statements? assign a = 1'b0; assign b = 1'b1; verilog Share Cite Follow edited Aug 1, 2014 at 16:14 stanri 5,382 2 29 56

  10. Are '0' and '1'b0' different in verilog?? (using Synopsys DC)

    30 Helped 0 Reputation 0 Reaction score 0 Trophy points 6 Activity points 263 Are '0' and '1'b0' different in verilog using synopsys DC?? When i used '0' in Xilinx synthesis tool (ISE and Vivado), there was no error. Using synopsys DC, I got elaborate error using verilog code which is running well in Xilinx tool.

  11. Difference between 1 and 1'b1 in Verilog

    1'b1 is an binary, unsigned, 1-bit wide integral value. In the original verilog specification, 1 had the same type as integer.It was signed, but its width was unspecified. A tool could choose the width base on its host implementation of the int type.. Since Verilog 2001 and SystemVerilog 2005, the width of integer and int was fixed at 32-bits. However, because of this original unspecified ...

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    Microsoft PowerPoint - L03_Verilog v2.pptx. Intro to Verilog. • Wires - theory vs reality (Lab1) • Hardware Description Languages. • Verilog -- structural: modules, instances -- dataflow: continuous assignment -- sequential behavior: always blocks -- pitfalls -- other useful features. Reminder: Lab #1 due by 9pm tonight.

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    2 Answers Sorted by: 2 Nothing says that you always need to specify all the zeros in binary base. In fact you can write it like this: reg [31:0] COUNT = 32'd0; ....using a decimal base. The Verilog will extend that decimal zero out to the specified 32 bit width. Share Cite Follow answered Feb 11, 2017 at 10:24 Michael Karas 57.2k 3 71 138 1

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  18. Please explain the following Verilog code of a D flip flop?

    1'b0 is Verilog syntax for a constant value that is a one bit number expressed in binary format with a value of zero. A bit value of one would be expressed as 1'b1. Similarly a four bit value in binary that is equivalent magnitude to a decimal value of 11 could be written as 4'b1011.

  19. Assigning values in Verilog: difference between assign, <= and

    18 I have just started learning Verilog and I've seen these three lines from different sources. I am confused about the difference between the three: c <= a&b; assign c = ~a; c = 1'b0; These lines seem to assign a value to c but what's the difference? Thanks. verilog assign Share Improve this question Follow asked Dec 12, 2014 at 2:03 dringx

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    2 Answers Sorted by: 5 'b0 -- is an unsized literal and its width is 32-bits (32'b0). So, there are 32-bits of zeros. '0 -- is a one-bit unsized constant and is a system verilog syntax used to make sure that there are as many zeros as needed in the context of an expression.

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