Verilog Blocking & Non-Blocking

Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

Note that there are two initial blocks which are executed in parallel when simulation starts. Statements are executed sequentially in each block and both blocks finish at time 0ns. To be more specific, variable a gets assigned first, followed by the display statement which is then followed by all other statements. This is visible in the output where variable b and c are 8'hxx in the first display statement. This is because variable b and c assignments have not been executed yet when the first $display is called.

In the next example, we'll add a few delays into the same set of statements to see how it behaves.

Non-blocking

Non-blocking assignment allows assignments to be scheduled without blocking the execution of following statements and is specified by a symbol. It's interesting to note that the same symbol is used as a relational operator in expressions, and as an assignment operator in the context of a non-blocking assignment. If we take the first example from above, replace all = symobls with a non-blocking assignment operator , we'll see some difference in the output.

See that all the $display statements printed 'h'x . The reason for this behavior lies in the way non-blocking assignments are executed. The RHS of every non-blocking statement of a particular time-step is captured, and moves onto the next statement. The captured RHS value is assigned to the LHS variable only at the end of the time-step.

So, if we break down the execution flow of the above example we'll get something like what's shown below.

Next, let's use the second example and replace all blocking statements into non-blocking.

Once again we can see that the output is different than what we got before.

If we break down the execution flow we'll get something like what's shown below.

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Blocking vs. Nonblocking in Verilog

The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic. In software, all assignments work one at a time. So for example in the C code below:

The second line is only allowed to be executed once the first line is complete. Although you probably didn’t know it, this is an example of a blocking assignment. One assignment blocks the next from executing until it is done. In a hardware description language such as Verilog there is logic that can execute concurrently or at the same time as opposed to one-line-at-a-time and there needs to be a way to tell which logic is which.

<=     Nonblocking Assignment

=      Blocking Assignment

The always block in the Verilog code above uses the Nonblocking Assignment, which means that it will take 3 clock cycles for the value 1 to propagate from r_Test_1 to r_Test_3. Now consider this code:

See the difference? In the always block above, the Blocking Assignment is used. In this example, the value 1 will immediately propagate to r_Test_3 . The Blocking assignment immediately takes the value in the right-hand-side and assigns it to the left hand side. Here’s a good rule of thumb for Verilog:

In Verilog, if you want to create sequential logic use a clocked always block with Nonblocking assignments. If you want to create combinational logic use an always block with Blocking assignments. Try not to mix the two in the same always block.

Nonblocking and Blocking Assignments can be mixed in the same always block. However you must be careful when doing this! It’s actually up to the synthesis tools to determine whether a blocking assignment within a clocked always block will infer a Flip-Flop or not. If it is possible that the signal will be read before being assigned, the tools will infer sequential logic. If not, then the tools will generate combinational logic. For this reason it’s best just to separate your combinational and sequential code as much as possible.

One last point: you should also understand the semantics of Verilog. When talking about Blocking and Nonblocking Assignments we are referring to Assignments that are exclusively used in Procedures (always, initial, task, function). You are only allowed to assign the reg data type in procedures. This is different from a Continuous Assignment . Continuous Assignments are everything that’s not a Procedure, and only allow for updating the wire data type.

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Blocking and Non-blocking Assignment in Verilog

  • Assignment is only done in procedural block(always ot initial block)
  • Both combintational and sequential circuit can be described.
  • Assignment can only possible to reg type irrespect of circuit type

Let's say we want to describe a 4-bit shift register in Verilog. For this, we are required to declare a 3-bit reg type variable.

The output of shift[0] is the input of shift[1], output of shift[1] is input of shift[2], and all have the same clock. Let's complete the description using both assignment operator.

Non-Blocking Assignment

When we do synthesis, it consider non-blocking assignment separately for generating a netlist. If we see register assignment in below Verilog code, all register are different if we consider non-blocking assignment separately. If you do the synthesis, it will generate 3 registers with three input/output interconnects with a positive edge clock interconnect for all register. Based on the Verilog description, all are connected sequentially because shift[0] is assigned d, shift[1] is assigned shift[0], and shift[2] is assigned shift[1].

Blocking Assignment

If we use blocking assignment and do the syhtheis, the synthesis tool first generate netlist for first blocking assignment and then go for the next blocking assignment. If in next blocking assignment, if previous output of the register is assigned to next, it will generate only a wire of previously assigned register.

In below Verilog code, even though all looks three different assignment but synthesis tool generate netlist for first blocking assigment which is one register, working on positive edge of clock, input d and output shift[0]. Since blocking assignment is used, for next blocking assignment, only wire is generated which is connected to shift[0]. Same is for next statement a wire is generated which is connected to shift[0].

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Procedural Assignments

In the dataflow modeling, a continuous assignment statement is discussed where LHS expression is always updated for changes in RHS expression. Refer to c ontinuous assignment for more details. In the case of procedural assignment, the LHS variable remains unchanged until the same value is updated by the next procedural statement.

  • RHS expression can be a value or an expression that evaluates to a value.
  • LHS expression can be reg, integer, real, time-variable, or memory element.
  • The procedural assignments can be placed inside procedural blocks like initial and always blocks. They can also be placed inside tasks and functions. 
  • The procedural assignments can also be placed directly inside a module while declaring a variable. (Ex. reg [3:0] i_data = 4’h7)

There are two types of procedural assignments and both of them are widely used in the designs written in the Verilog language.

  • Blocking assignments
  • Non-blocking assignments

Blocking Assignments

The blocking assignment statements are executed sequentially by evaluating the RHS operand and finishes the assignment to LHS operand without any interruption from another Verilog statement. Hence, it blocks other assignments until the current assignment completes and is named as “blocking assignment”. 

An equal ‘=’ is used as a symbol for the blocking assignment operator.

A blocking assignment does not block the execution of a statement in another procedural block. For example, two initial blocks start execution at the same simulation time. A blocking assignment in the first initial block does not block execution in another initial block.

Race around condition: A problem with blocking assignment

If a variable is used in LHS of blocking assignment in one procedural block and the same variable is used in RHS of another blocking assignment in another procedural block. The race-around condition can occur as an order of execution is unknown if both statements are scheduled at the same simulation time.

In this example, 

Since procedural blocks (both initial and always) can be executed in any order.

A. If the first initial block executed before the second initial block then 

  • The value of y will be updated as 4‘h5 in the first initial block
  • The value of data will be updated as 4‘h5 in the second initial block

B. If the second initial block executed before the first initial block then 

  • The value of data will be updated as 4‘h3 in the second initial block
  • The value of y will be updated as 4‘h3 in the first initial block

Verilog Tutorials

Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

There are Two types of Procedural Assignments in Verilog.

  • Blocking Assignments
  • Nonblocking Assignments

To learn more about Delay: Read  Delay in Assignment (#) in Verilog

Blocking assignments

  • Blocking assignments (=) are done sequentially in the order the statements are written.
  • A second assignment is not started until the preceding one is complete. i.e, it blocks all the further execution before it itself gets executed.

Blocking

Non-Blocking assignments

  • Nonblocking assignments (<=), which follow each other in the code, are started in parallel.
  • The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure.
  • The transfer to the left hand side is made according to the delays. An intra- assignment delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking. However normal delays are cumulative and will delay the output.
  • Non-blocking schedules the value to be assigned to the variables but the assignment does not take place immediately. First the rest of the block is executed and the assignment is last operation that happens for that instant of time.

Non_Blocking

To learn more about Blocking and Non_Blocking Assignments: Read Synthesis and Functioning of Blocking and Non-Blocking Assignments

The following example shows  interactions  between blocking  and non-blocking for simulation only (not for synthesis).

Mixed

For Synthesis (Points to Remember):

  • One must not mix “<=” or “=” in the same procedure.
  • “<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk..) type procedures.
  • “=” best corresponds to what c/c++ code would do; use it for combinational procedures.

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  • Synthesis and Functioning of Blocking and Non-Blocking Assignments.
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Verification Guide

SystemVerilog Blocking assignment

Blocking assignment.

Blocking assignment statements execute in series order. Blocking assignment blocks the execution of the next statement until the completion of the current assignment execution.

Blocking assignment example

In Below Example, a and b is initialized with value 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment value of a = 15 and b=20.

Simulator Output:

blocking assignment verilog

Blocking assignment example-2

In Below Example, a and b are initialized with value 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b. After assignment value of a = 15 and b = 20.

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COMMENTS

  1. Verilog Blocking & Non-Blocking

    Blocking assignment statements are assigned using = and are executed one after the other in a procedural block. However, this will not prevent execution of statments that run in a parallel block.

  2. Difference between blocking and nonblocking assignment Verilog

    3 Answers Sorted by: 28 was fairly sure that nonblocking assignments were sequential while blocking assignments were parallel. Blocking assignment executes "in series" because a blocking assignment blocks execution of the next statement until it completes. Therefore the results of the next statement may depend on the first one being completed.

  3. PDF I. Blocking vs. Nonblocking Assignments

    • Verilog supports two types of assignments within blocks, with subtly different behaviors. always Blocking assignment: evaluation and assignment are immediate always @ (a or b or c) begin x = a | b; y = a ^ b ^ c; z = b & ~c; 1. Evaluate a | b, assign result to 2. Evaluate a^b^c, assign result to 3. Evaluate b&(~c), assign result to x y z end

  4. How to interpret blocking vs non blocking assignments in Verilog

    6 Answers Sorted by: 44 The conventional Verilog wisdom has it all wrong. There is no problem with using blocking assignments for a local variable. However, you should never use blocking assignments for synchronous communication, as this is nondeterministic.

  5. Blocking and Nonblocking Assignments in Verilog

    Blocking and Nonblocking Assignments in Verilog Blocking vs. Nonblocking in Verilog The concept of Blocking vs. Nonblocking signal assignments is a unique one to hardware description languages. The main reason to use either Blocking or Nonblocking assignments is to generate either combinational or sequential logic.

  6. Blocking and Non-blocking Assignment in Verilog

    When working with behavioural modeling in Verilog, there are two types of assigment which is known as blocking and non blocking assigment and both of them there is a operator, '=' operator for blocking assignment and '<=' operator for non blocking assigment.

  7. Blocking Assignments

    The blocking assignment statements are executed sequentially by evaluating the RHS operand and finishes the assignment to LHS operand without any interruption from another Verilog statement. Hence, it blocks other assignments until the current assignment completes and is named as "blocking assignment".

  8. Blocking (immediate) and Non-Blocking (deferred) Assignments in Verilog

    There are Two types of Procedural Assignments in Verilog. Blocking Assignments Nonblocking Assignments To learn more about Delay: Read Delay in Assignment (#) in Verilog Blocking assignments Blocking assignments (=) are done sequentially in the order the statements are written.

  9. PDF Understanding Verilog Blocking and Nonblocking Assignments

    An edge-sensitive intra-assignment timing control permits a special use of the repeat loop. The edge sensitive time control may be repeated several times before the delay is completed. Either the blocking or the non-blocking assignment may be used. always always @(IN) @(IN) OUT OUT <= <= repeat.

  10. Blocking And Nonblocking In Verilog

    Blocking Statements: A blocking statement must be executed before the execution of the statements that follow it in a sequential block. In the example below the first time statement to get executed is a = b followed by. Nonblocking Statements: Nonblocking statements allow you to schedule assignments without blocking the procedural flow.

  11. PDF Advanced Verilog

    Always Block An always block is an example of a procedure. The procedure executes a set of assignments when a defined set of inputs change. 2:1 mux Always Block Module mux_2_1(a, b, out, sel); input a, b, sel; output out; reg out; always @ (a or b or sel) begin if (sel) out = a; else out = b; end endmodule Declare Module and IO as before.

  12. Code Crafting: The Art of Blocking and Non-Blocking Assignments in Verilog

    Procedural Statements in Verilog, such as blocking and non-blocking assignments, are categorized as elements of procedural blocks, such as 'always' and 'initial.'

  13. Understanding the Differences Between Blocking and Non-Blocking

    This episode provides a comprehensive analysis of the key differences between blocking and non-blocking assignments in Verilog. The host begins by introducin...

  14. PDF Blocking and Non-blocking Assignments in Explicit and Implicit Style

    Verilog provides two kinds of behavioral assignment: the blocking assignment (=), which is similar to software as-signment statements found in most conventional pro-gramming languages, and the non-blocking assignment (<=), which is the more natural assignment statement to describe many hardware systems, especially for syn-thesis.

  15. SystemVerilog Blocking assignment

    Blocking assignment blocks the execution of the next statement until the completion of the current assignment execution. Blocking assignment example In Below Example, a and b is initialized with value 10 and 15 respectively, after that b is being assigned to a (a value will become 15), and value 20 is assigned to b.

  16. Using blocking assignments to infer flip-flops in Verilog

    Using blocking assignments to infer flip-flops in Verilog Asked 11 years, 7 months ago Modified 11 years, 7 months ago Viewed 5k times 3 I have read "Nonblocking Assignments in Verilog Synthesis, Coding Styles that Kill!" by Clifford Cummings.

  17. <= Assignment Operator in Verilog

    "<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators.

  18. Why we need non-blocking assignments in Verilog?

    I understand that blocking assignments execute in a sequential manner,whereas it is possible to assign values concurrently using non-blocking statements. My question is, why was non-blocking assignments included in Verilog. I can think of the following example to give weight to my statement. Using blocking assignment: always@(posedge) a = b ...

  19. Verilog Blocking and Non-blocking

    Verilog supports blocking and non-blocking assignments statements within the always block with their different behaviors. The blocking assignment is similar to software assignment statements found in most popular programming languages.