verilog assign value to vector

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Vector assignment in Verilog

It is my first attempt to use verilog. I have defined an 8-bit bidirectional port, a data register and a data direction register in the following way:

It works perfectly, however, I'm sure, there must be an easier way to accomplish the same result.

I have tried with a for cycle:

as well as assigning the whole vector at once:

without any result. Thanks for any help.

You want a generate-for loop.

This gets unrolled into what you originally wrote.

• Thank you very much. I didn't know about generate-for loop, but after your answer and a bit more reading around I think I've got the difference between loop evaluated at compile time vs. runtime. –  Luca Sep 20, 2017 at 3:42

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Assigning to a parameterized 2d Verilog array

I have a Verilog array defined as :

I want to assign every array element with a vector that is all ones: "11...1". I tried this but I get an error:

What's the correct syntax ?

• system-verilog

2 Answers 2

To assign unpacked 2d array in SystemVerilog with a single line:

Verilog cannot be done in a single line. It must use a for-loop:

• \$\begingroup\$ Suppose: num_elements = 4 element_width = 8 Making it more complicated I want each element to get "0xFA" So now - my ONLY option is to use the for-loop approach ? There's no way to do it in a single line like in VHDL ? some_array <= ( others => ( others => x"FA" ) ) ; \$\endgroup\$ –  shaiko Sep 7, 2020 at 9:02
• 1 \$\begingroup\$ @shaiko the SystemVerilog '{default: } approach will still work. Refer to the SystemVerilog LRM \$\endgroup\$ –  Greg Sep 7, 2020 at 17:30
• \$\begingroup\$ It'll work for packed as well as unpacked array ? \$\endgroup\$ –  shaiko Sep 7, 2020 at 17:45

Since some_array is all packed, you can do

• \$\begingroup\$ What if it was unpacked ? \$\endgroup\$ –  shaiko Sep 6, 2020 at 20:10
• \$\begingroup\$ I'm looking for a syntax to assign each array element individually...similar to what I wrote in my example. \$\endgroup\$ –  shaiko Sep 6, 2020 at 20:34
• 1 \$\begingroup\$ In your example, each element is a single bit. You might want to check out the default: clause of an array assignment pattern \$\endgroup\$ –  dave_59 Sep 6, 2020 at 22:55

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Verilog Assignments

Variable declaration assignment, net declaration assignment, assign deassign, force release.

• Procedural continuous

Legal LHS values

An assignment has two parts - right-hand side (RHS) and left-hand side (LHS) with an equal symbol (=) or a less than-equal symbol (<=) in between.

The RHS can contain any expression that evaluates to a final value while the LHS indicates a net or a variable to which the value in RHS is being assigned.

Procedural Assignment

Procedural assignments occur within procedures such as always , initial , task and functions and are used to place values onto variables. The variable will hold the value until the next assignment to the same variable.

The value will be placed onto the variable when the simulation executes this statement at some point during simulation time. This can be controlled and modified the way we want by the use of control flow statements such as if-else-if , case statement and looping mechanisms.

An initial value can be placed onto a variable at the time of its declaration as shown next. The assignment does not have a duration and holds the value until the next assignment to the same variable happens. Note that variable declaration assignments to an array are not allowed.

If the variable is initialized during declaration and at time 0 in an initial block as shown below, the order of evaluation is not guaranteed, and hence can have either 8'h05 or 8'hee.

Procedural blocks and assignments will be covered in more detail in a later section.

Continuous Assignment

This is used to assign values onto scalar and vector nets and happens whenever there is a change in the RHS. It provides a way to model combinational logic without specifying an interconnection of gates and makes it easier to drive the net with logical expressions.

Whenever b or c changes its value, then the whole expression in RHS will be evaluated and a will be updated with the new value.

This allows us to place a continuous assignment on the same statement that declares the net. Note that because a net can be declared only once, only one declaration assignment is possible for a net.

Procedural Continuous Assignment

• assign ... deassign
• force ... release

This will override all procedural assignments to a variable and is deactivated by using the same signal with deassign . The value of the variable will remain same until the variable gets a new value through a procedural or procedural continuous assignment. The LHS of an assign statement cannot be a bit-select, part-select or an array reference but can be a variable or a concatenation of variables.

These are similar to the assign - deassign statements but can also be applied to nets and variables. The LHS can be a bit-select of a net, part-select of a net, variable or a net but cannot be the reference to an array and bit/part select of a variable. The force statment will override all other assignments made to the variable until it is released using the release keyword.