vhdl assign to unsigned

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VHDL assigning literals

I'm trying to use unsigned integers in VHDL with well defined bit widths. It seems VHDL does not like me trying to assign literal values to these types defined as:

But in my IDE (Quartus), I get a complaint "UNSIGNED type does not match integer literal." I also get complaints for adding numbers to types defined like this. Whats the preferred change I need to make?

• unsigned-integer

3 Answers 3

See other answers, and note that for non-zero literals, you probably want to do something like:

Substitute a literal for n . This works for n =0 too, of course, but it's not as tidy as (others => '0') .

• LCD_DATA'LENGTH isn't available until after the semicolon. IEEE Std 1076-1993 10.3 Notes "2—The rules defining immediate scope, hiding, and visibility imply that a reference to an identifier, character literal, or operator symbol within its own declaration is illegal (except for design units). The identifier, character literal, or operator symbol hides outer homographs within its immediate scope—that is, from the start of the declaration. On the other hand, the identifier, character literal, or operator symbol is visible only after the end of the declaration (again, except for design units)." –  user1155120 Mar 18, 2014 at 23:02
• For -2008 that's Section 12.3 Visibility, same Note 2. –  user1155120 Mar 18, 2014 at 23:16
• The original erroneous answer provided variable LCD_DATA: unsigned(19 downto 0) := to_unsigned(n, LCD_DATA'length); Essentially something isn't available until it is declared and the declaration is variable_declaration ::= [ shared ] variable identifier_list : subtype_indication [ := expression ] ; , which is where the after the semicolon comment comes from. See IEEE Std 1076-1993 4.3.1.3 (6.4.2.4 -2008) Variable declarations. –  user1155120 Mar 18, 2014 at 23:26
• Yeah, I'm so used to using that construct in processes, etc., I forgot it was illegal in declarations. –  fru1tbat Mar 19, 2014 at 13:53

And for the 2nd part of your question while adding number of this type.

Check whether you have used above libraries in the code or not.

unsigned is related to std_ulogic, where the value for an element would be '0'.

which provides an aggregate for the default assignment with all elements set to '0'.

You can't assign a single element of integer type to an array of std_ulogic elements.

You can add signed or unsigned to a natural (unsigned) or integer (signed) using "+" functions defined in package numeric_std:

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How to use Signed and Unsigned in VHDL

The signed and unsigned types in VHDL are bit vectors, just like the std_logic_vector type. The difference is that while the std_logic_vector is great for implementing data buses, it’s useless for performing arithmetic operations.

If you try to add any number to a std_logic_vector type, ModelSim will produce the compilation error: No feasible entries for infix operator “+” . This is because the compiler doesn’t know how to interpret this collection of bits that the vector is.

This blog post is part of the Basic VHDL Tutorials series.

We must declare our vector as signed or unsigned for the compiler to treat it as a number.

The syntax for declaring signed and unsigned signals is:

Just like with std_logic_vector, the ranges can be to or downto any range. But declaring signals with other ranges than downto 0 is so uncommon, that spending any more time on the subject would only serve to confuse us. The initial value is optional, by default it’s 'U' for all bits.

We have already been using the integer type for arithmetic operations in previous tutorials. So why do we need the signed and unsigned types? For most, digital designers like to have more control of how many bits a signal actually uses.

Also, signed and unsigned values wrap around, while the simulator will throw a run-time error if an integer is incremented beyond bounds. Finally, signed and unsigned can have other values like 'U' and 'X' , while integers can only have number values. These meta-values can help us discovering errors in our design.

In this video we learn how signed and unsigned signals behave alike, and how they behave differently:

The final code we created in this tutorial:

The waveform window in ModelSim, zoomed in on the interesting parts:

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The radix of all signals in the waveform are set to hexadecimal so that we can compare them equally.

In the wrapping counter example, we see that the signed and unsigned signals behave exactly the same way. Both UnsCnt and SigCnt start at 0, and are incremented one-by-one up to FF. Hex FF (decimal 255) is the largest value our 8-bit signals can hold. Therefore, the next increment wraps both of them back to 0.

We created the two 4-bit signals Uns4 and Sig4 , and gave them both an initial value of “1000”. We can see from the waveform that they are both just hex 8 (binary 1000).

The last two 8-bit signals we created were Uns8 and Sig8 . We can see from the waveform that their initial values are 0, as one would expect. But from there, they behave differently! Apparently, signed and unsigned types made a difference when adding two signals of different lengths.

This is because of something known as sign extension . Adding positive or negative numbers stored in vectors of equal length, is the same operation in digital logic. This is because of how two’s complement works. If the vectors are of different lengths, the shortest vector will have to be extended.

The unsigned 4-bit binary number “1000” is decimal 8, while the signed 4-bit number “1000” is decimal -8. The “1” at the left-most place of the signed number indicates that this is a negative number. Therefore, the two 4-bit signals are sign extended differently by the compiler.

This is a visualization of how sign extension creates the differing values for the Uns8 and Sig8 signals:

• Signals of signed and unsigned type are vectors that can be used in arithmetic operations
• Signals of signed and unsigned type will overflow silently
• Sign extension may create differing results for signed and unsigned types

Go to the next tutorial »

I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

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I am confused by the article. To quote your text,

“The unsigned 4-bit binary number “1000” is decimal 8, while the signed 4-bit number “1000” is decimal -4”

Seems to me that “1000” in signed 2’s complement would be -8, not -4…right?

You are correct! I changed the text to -8 now. Fortunately I said -8 in the video 🙂 Thank you for pointing that out.

Thank you Jonas very much for your informative article! Perhaps you could also comment on this approach?

With those in place we can do arithmetic and comparisons on std_logic_vectors directly. For example:

There is one disadvantage that all signals in the same file will be treated as signed or unsigned. Perhaps this approach is not the best way in any case.

Your comment got me thinking about these packages. Even though I’ve been aware of them for quite some time, I don’t recall seeing them used in any projects which I have participated in. Why is that?

I believe this article by Sigasi sums up the main reason: https://insights.sigasi.com/tech/deprecated-ieee-libraries/

The packages are vendor specific extensions, and not really part of the IEEE library.

Even though you save time by implicitly casting the std_logic_vector, I’m not convinced that it will be and advantage in the long run. It becomes difficult for other developers to jump in and understand what the code does.

You would have to look at the imports in the head of the file to see what your code line does. If the std_logic_unsigned is imported, the result may be something else than if std_logic_signed was used. I find it confusing, but that’s just my personal opinion.

Thank you Jonas, I agree with you.

Hello mr Jensen , thank you for all the materials which are huge help. Got one question, How can we determine some bits of an unsigned signal? for example:

But how about “0100”? is there any way to alter desired bits without writing the whole string? Gets difficult when width of signals isn’t a small integer!

Sure, you can achieve that like this:

The range of values for signed 8 bit variable is given by the formula -2^(n-1) to 2^(n-1) – 1, n = 8 = -2^7 to 2^7 -1 = -128 to 127.

The range of values for unsigned 8 bit variable is given by the formula 2(^n) – 1, n = 8 = 2^8 -1 = 256.

For the counter of data type unsigned initialized to zero, the maximum count values is 0xff = 256 For the counter of data type signed initialized to zero, the maximum count value is 0x7f = 127

Do you agree?

Br, Lawrence

This statement is correct for signed types: -2^(n-1) to 2^(n-1) – 1, n = 8 = -2^7 to 2^7 -1 = -128 to 127.

However, the range for unsigned will be 0 to 2^8 -1 = 255 (I’m sure you meant to write 255 and not 256 since you got the formula right).

VHDL signals always default to the leftmost value if you don’t initialize them. For std_logic, which is based on the enumerated type std_ulogic, this is the ‘U’ value.

However, the signed VHDL type is an array of std_logic’s. Therefore, the default initial value of a signed in VHDL isn’t a numeric value. It’s an array of ‘U’s.

Integers, on the other hand, behave as you were thinking the signed would. But the caveat is that it depends on which direction (to/downto) you gave the integer signal or variable when declaring it.

These are some examples of initial/default values:

I know it seems confusing, but it really isn’t. You just have to remember that the default initial value will always be the leftmost possible value of your type, regardless if it’s declared using “to” or “downto” direction.

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Signed vs. Unsigned in VHDL

All Digital Designers must understand how math works inside of an FPGA or ASIC. The first step to that is understanding how signed and unsigned signal types work. Signed and unsigned types exist in the numeric_std package, which is part of the ieee library. It should be noted that there is another package file that is used frequently to perform mathematical operations: std_logic_arith . However, std_logic_arith is not an official ieee supported package file and it is not recommended for use in digital designs.

A signal that is defined as type signed means that the tools interpret this signal to be either positive or negative. A signal that is defined as type unsigned means that the signal will be only positive. Internally, the FPGA will use Two’s Complement representation. For example, a 3-bit signal can be interpreted according to the table below:

Are you confused yet? You should be, this is not intuitive! Let’s look at an example which will hopefully clear things up. The file below tests out how signed unsigned works. What needs to be understood is that whether or not the signals are defined as signed or unsigned does not affect how the actual binary math is performed.

For example: For two signed vectors 10001 + 00010 the answer is still 10011, BUT it’s the interpretation of the result that is different. For the unsigned case, the answer (10011) represents 19. For the signed case, the answer (10011) represents -13.

Simulation Output of Signed vs. Unsigned in Decimal

Simulation Output of Signed vs. Unsigned in Hex

Compare the two modelsim screenshots above. In the first you can see that the results of the mathematical functions are exactly the same when represented in hex. It’s the interpretation of the results that is different. This can be seen by looking at the bottom screenshot. When Modelsim displays the results in decimal it interprets some of them as negative numbers. When using signed and unsigned types you must be very careful! Hopefully you understand this topic a little better. I feel like this is an area that many digital designers struggle with, so if there is something that you do not fully understand please send me an email via the Contact Link on the Sidebar and I will try to make it clearer.

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mlefevre (Customer) asked a question.

• constant SOME_GENERIC_VALUE : integer := 521 ;
• signal offset : signed ( 47 downto 0 ) := to_signed ( 88555363 * SOME_GENERIC_VALUE , 48 );
• Simulation & Verification

mlefevre (Customer)

• signal offset : signed ( 47 downto 0 ) := to_signed ( 88555363 , 37 )*
• to_signed ( SOME_GENERIC_VALUE , 11 );

dprasad (Customer)

-------------------------------------------------------------------------------------------------

geoffbarnes (Customer)

paebbels (Customer)

• type INT_16 is range - 32768 to 32767 ;
• type INT_64 is range - 2 ** 63 to 2 ** 63 - 1 ;

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Convert To Unsigned in VHDL?

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Convert To Unsigned in VHDL

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VHDL is a type sensitive language - converting ( a signed number or a non-number such as std_logic_vector ) to unsigned is achieved via casting.

std_logic_vector to unsigned: * data_u <= unsigned(data_slv); bit_vector to unsigned: * data_u <= unsigned(data_bv); But you need to use a proper package (numeric_std, numeric_bit, std_logic_arith) To convert from integer to unsigned: * to_unsigned(data_int, size) - using either numeric_bit or numeric_std * conv_unsigned(data_int, size) - using std_logic_arith Note: It is better to use numeric_std instead std_logic_arith + std_logic_unsigned/signed because numeric_std - is the standard IEEE library and it include all that you need in signed/unsigned arithmetic while others are vendor specific extensions from Synopsys and Mentor Graphics.

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array assignment in vhdl with signed numbers

• Thread starter 214
• Start date Mar 22, 2016
• Mar 22, 2016

Junior Member level 2

i have to declare an array with numbers like (for eg. 4.344, 2.55, 0.56, 6.33) ... how to initialize this type of array.... TYPE buf_ary_d IS ARRAY (...????) OF SIGNED(7 DOWNTO 0); what to write inside bracket  

amit.kumar11

Member level 5.

Hi, Inside bracket is the no of element in the array. ex: type array_type2 is array (0 to 3) of std_logic_vector(11 downto 0); Here array is of 4 element with each having 12 bits. Amit  

TYPE buf_ary IS ARRAY(NATURAL RANGE <>) OF UNSIGNED(7 DOWNTO 0); what does NATURAL RANGE <> mean ?????  

Super Moderator

Natural number range, any subrange of 0 to maxint or maxint downto 0. You are using this declaration to define a type without specifying the actual range. The range will be specified when referencing the type declaration. Like below: Code: TYPE buf_ary IS ARRAY(NATURAL RANGE <>) OF UNSIGNED(7 DOWNTO 0); SIGNAL buf1 : buf_ary(0 to 5); SIGNAL buf2 : buf_ary(13 downto 2);  

Advanced Member level 4

'left and 'right are natual numbers -- the subset of VHDL integers that are not negative. ( n >= 0). The second part is that decimal values don't have a fully standard representation. VHDL2008 supports fixed point values, were indicies below 0 indicate "fractional bits". for example, bit index 0 represents 1. bit index -1 represents 0.5. index -2 represents 0.25. This is done with sfixed. In previous versions, you would need to use signed, but then keep track of where the fractional bits were.  

sorry....can you make this explanation simpler.....i did not understand this  

Numbers like 4.344, 2.55, 0.56, 6.33 are not unsigned. Unsigned can only take integer values. You can scale the numbers to unsigned by multiplying it with a factor of your choice, preferably 2^N, and rounding to nearest integer. Or read about IEEE fixed point package.  

TYPE buf_ary_d IS ARRAY (NATURAL RANGE <>) OF SIGNED(7 DOWNTO 0); will it work for my case ???  

I overlooked that you want signed, not unsigned. You could e.g. use a scaling factor of 16. Code: CONSTANT carray: buf_ary_d(0 to 3) := ( to_signed(integer(16.0*4.344),8), to_signed(integer(16.0*2.55),8), to_signed(integer(16.0*0.56),8), to_signed(integer(16.0*6.33),8)); - - - Updated - - - That's without rounding to nearest integer  

TrickyDicky

Advanced member level 7.

vGoodtimes said: 'left and 'right are natual numbers -- the subset of VHDL integers that are not negative. ( n >= 0). The second part is that decimal values don't have a fully standard representation. VHDL2008 supports fixed point values, were indicies below 0 indicate "fractional bits". for example, bit index 0 represents 1. bit index -1 represents 0.5. index -2 represents 0.25. This is done with sfixed. In previous versions, you would need to use signed, but then keep track of where the fractional bits were. Click to expand...

my point on 'left and 'right was a response to "what is natural range <>". I had started the response before your reply to the same question. (also, you don't need to anchor to 0 on either side)  

Member level 2

214 said: i have to declare an array with numbers like (for eg. 4.344, 2.55, 0.56, 6.33) ... how to initialize this type of array.... TYPE buf_ary_d IS ARRAY (...????) OF SIGNED(7 DOWNTO 0); what to write inside bracket Click to expand...

You can't use numbers with type "real" for synthesys, only in testbench. Click to expand...

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problem with unsigned vs std_logic_vector

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